1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a memory device, the architecture of which is easily modified, having high redundancy flexibility, and low power consumption.
2. Description of the Related Art
Today""s multimedia development often requires having several specific applications simultaneously. For this and other reasons, the speed of operation of the CPU of high-performance computer systems has constantly increased, and also for this reason SDRAMs having a high bandwidth and a multi-bank structure have been developed.
Most SDRAMs currently used have a maximum frequency of about 133 MHz, which is considerably low compared to the CPU operation speed. Also, since a memory cell of a SDRAM is composed of one transistor and one capacitor like a memory cell of a DRAM, there is a certain limitation in reducing the time required for writing and reading data. The SDRAM generally has an internal four-bank structure, but the bandwidth of the SDRAM is not large enough to process the CPU-required data. Thus, a bottleneck phenomenon occurs in many computer systems.
In order to avoid this and further prevent the performance of computer systems from being degraded, the SDRAM bandwidth is generally increased by a prefetch method. In the prefetch method, (nxc3x97m) data obtained by multiplying n external DQ pads by m data in a memory cell array block is read all at once in a reading operation of the SDRAM. Next, m data are sequentially output in each of the n external DQ pads in a pipeline type operation by synchronizing the (nxc3x97m) data with an external clock signal. Also, data is received m times from each of the n external DQ pads in the writing operation of the SDRAM and written in a memory cell array all at once.
However, by increasing the bandwidth using the prefetch method, the column redundancy flexibility is reduced. This is because in column redundancy, if a memory cell selected from one memory bank is defective, bit lines of this defective memory cell are replaced with bit lines of a redundant memory cell. However, if the number of memory cells selected at a time increases to m, it is insufficient to merely replace the defective memory cells with limited redundant memory cells.
A way of overcoming reducing the column redundancy flexibility is by increasing a page size. The page size represents the number of memory cells activated by a one-time row access. In other words, the page size represents the number of sense amplifiers operated by one word line. The memory cells operated by one word line are set to be activated in two memory banks, and thus the column redundancy flexibility in each of the memory banks is not changed. However, this method of increasing the page size consumes a large amount of power since sense amplifiers in two memory banks operate.
Accordingly, a memory device capable of increasing redundancy flexibility and reducing power consumption is required.
To solve the above-described problems, it is a first object of the present invention to provide a memory device capable of maintaining uniform redundancy flexibility and reducing power consumption.
It is a second object of the present invention to provide a memory system having a memory module with the memory device.
In accordance with the invention, there is provided a semiconductor memory device including first and second memory architectures. The first memory architecture has p banks, a page size of m/2 bytes of m/2 memory cells connected to one word line in each of the banks, and n/2 data terminals DQ. The second memory architecture has p banks, a page size of m bytes, and n data terminals.
In one embodiment, one of the first memory architecture and the second memory architecture is selected using an option process.
A semiconductor memory device according to another embodiment includes first and second memory architectures. The first memory architecture has p banks, a page size of m/2 bytes of m/2 memory cells connected to one word line in each of the memory banks, and n/2 data terminals DQ. The second memory architecture has p/2 banks, a page size of m bytes, and n data terminals.
If the first memory architecture includes p/2 memory banks, the second memory architecture includes p memory banks.
Preferably, the option process is realized by a bonding, a mask pattern, or a fuse.
In accordance with another aspect of the invention, there is provided a memory system. The memory system includes a memory controller, a first memory module, and a second memory module. The first memory module is connected to the memory controller via data bus lines and includes i memory devices. The second memory module is connected to the memory controller via the data bus lines and includes i/2 memory devices. Each of the memory devices of each of the first and second memory modules includes first and second memory architectures. The first memory architecture is selected by the memory devices of the first memory module, and the second memory architecture is selected by the memory devices of the second memory module. The first memory architecture has p memory banks, a page size of m/2 bytes of m/2 memory cells connected to one word line in each of the memory banks, and n/2 data terminals DQ. The second memory architecture has p or p/2 memory banks, a page size of m bytes, and n data terminals DQ.
Preferably, the option process is realized by a bonding, a mask pattern, or a fuse.
The page size and the number of memory banks are adjusted by a design option. Thus, redundancy flexibility can increased and power consumption can reduced.